Unique Chips and Systems

Series:
Computer Engineering Series
Published:
November 15, 2007 by CRC Press - 392 Pages
Editor(s):
Eugene John, The University of Texas, San Antonio, USA; Juan Rubio, Austin, Texas, USA

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Hardback
$119.95
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ISBN 9781420051742
Cat# 51741
 

Features

  • Describes the architecture and implementation of the TRIPS processor
  • Discusses the RACE-H™ architecture, the scalable DMA subsystem, programming tools, and a brief performance evaluation
  • Introduces the RASTER architecture, which consists of an FPGA logic cell that maximizes throughput and uses a routing-efficient method of inter-cell communication.
  • Presents the continuation-based Fuce multithreading processor
  • Compares two approaches that maximize the additional processing cores present on a single-chip multi-core processor for single single-thread performance
  • Explores two visualization applications that yield efficient methods for visualization, animation, and geometric processing of the shape
  • Analyzes the performance and characteristics of MSA software from the perspective of processor microarchitecture

    • Summary

    Which came first, the system or the chip? While integrated circuits enable technology for the modern information age, computing, communication, and network chips fuel it. As soon as the integration ability of modern semiconductor technology offers presents opportunities, issues in power consumption, reliability, and form-factor present challenges. The demands of emerging software applications can only be met with unique systems and chips. Drawing on contributors from academia, research, and industry, Unique Systems and Chips explores unique approaches to designing future computing and communication chips and systems.

    The book focuses on specialized hardware and systems as opposed to general-purpose chips and systems. It covers early conception and simulation, mid-development, application, testing, and performance. The chapter authors introduce new ideas and innovations in unique aspects of chips and system design, then go on to provide in-depth analysis of these ideas. They explore ways in which these chips and systems may be used in further designs or products, spurring innovations beyond the intended scopes of those presented. International in flavor, the book brings industrial and academic perspectives into focus by presenting the full spectrum of applications of chips and systems.

    Table of Contents

    Architecture and Implementation of the TRIPS Processor, S.W. Keckler, D. Burger, K. Sankaralingam, R. Nagarajan, R. McDonald, R. Desikan, S. Drolia, M.S. Govindan, P. Gratz, D. Gulati, H. Hanson, C. Kim, H. Liu, N. Ranganathan, S. Sethumadhavan, S. Sharif, and P. Shivakumar

    High -Performance Data Security in an x86 Processor, G. Henry, T. Parks, and T. Crispin

    ARM Cortex A8: A High Performance Processor for Low Power Applications, D. Williamson

    Rotated Array Clustered Extended Hypercube Processor: The RACE-H Processor, G.G. Pechanek, M. Stojancic, F. Barry, and N. Pitsianis

    A High-Throughput Self-Timed FPGA Core Architecture, B.C. Gaide and L.K John

    The Continuation Based Multithreading Processor, M. Izumi, S. Amamiya, T. Matsuzaki, and M. Amamiya

    A Study of a Processor with Dual Thread Execution Modes, R. Mameesh and M. Franklin

    Measurement Based Power Phase Analysis, W.L. Bircher and L.K. John

    Visualization by Subdivision: Two Applications for Future Graphics Platforms, C.T. John

    A Performance Analysis of Two-level Heterogeneous Systems on Wavefront Algorithms, D.J. Kerbyson and A. Hoisie

    Microarchitectural Characteristics and Implications of Alignment of Multiple Bioinformatics Sequences, T. Li

    Towards System-Level Fault-Tolerance Using Formal Methods and SoC Methodologies Evaluation of Delay Queues for a Ravenscar Kernel, K. Lundqvist

    Forward Error Correction for On-chip Interconnection Networks, P. Bhojwani, R. Singhal, G. Choi, and R. Mahapatra

    Alleviating Thermal Constraints while Maintaining Performance via Silicon-based On-Chip Optical Interconnects, N. Nelson, G. Briggs, M. Haurylau, G. Chen, H. Cgen, D.H. Albonesi, E.G. Friedman, and P.M. Fauchet

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