1st Edition

Spacer Engineered FinFET Architectures High-Performance Digital Circuit Applications

    154 Pages
    by CRC Press

    154 Pages 39 Color & 49 B/W Illustrations
    by CRC Press

    154 Pages 39 Color & 49 B/W Illustrations
    by CRC Press

    This book focusses on the spacer engineering aspects of novel MOS-based device–circuit co-design in sub-20nm technology node, its process complexity, variability, and reliability issues. It comprehensively explores the FinFET/tri-gate architectures with their circuit/SRAM suitability and tolerance to random statistical variations.

    Preface



    About the Authors



     





    Chapter 1 ◾ Introduction to Nanoelectronics



    Chapter 2 ◾ Tri-Gate FinFET Technology and Its Advancement



    Chapter 3 ◾ Dual-k Spacer Device Architecture and Its Electrostatics



    Chapter 4 ◾ Capacitive Analysis and Dual-k FinFET-Based Digital Circuit Design



    Chapter 5 ◾ Design Metric Improvement of a Dual-k–Based SRAM Cell



    Chapter 6 ◾ Statistical Variability and Sensitivity Analysis



     





    INDEX

    Biography

    Sudeb Dasgupta, Brajesh Kumar Kaushik, Pankaj Kumar Pal