2nd Edition

Digital Integrated Circuits Analysis and Design, Second Edition

By John E. Ayers Copyright 2010
    616 Pages 483 B/W Illustrations
    by CRC Press

    Exponential improvement in functionality and performance of digital integrated circuits has revolutionized the way we live and work. The continued scaling down of MOS transistors has broadened the scope of use for circuit technology to the point that texts on the topic are generally lacking after a few years.

    The second edition of Digital Integrated Circuits: Analysis and Design focuses on timeless principles with a modern interdisciplinary view that will serve integrated circuits engineers from all disciplines for years to come. Providing a revised instructional reference for engineers involved with Very Large Scale Integrated Circuit design and fabrication, this book delves into the dramatic advances in the field, including new applications and changes in the physics of operation made possible by relentless miniaturization.

    This book was conceived in the versatile spirit of the field to bridge a void that had existed between books on transistor electronics and those covering VLSI design and fabrication as a separate topic. Like the first edition, this volume is a crucial link for integrated circuit engineers and those studying the field, supplying the cross-disciplinary connections they require for guidance in more advanced work.

    For pedagogical reasons, the author uses SPICE level 1 computer simulation models but introduces BSIM models that are indispensable for VLSI design. This enables users to develop a strong and intuitive sense of device and circuit design by drawing direct connections between the hand analysis and the SPICE models.

    With four new chapters, more than 200 new illustrations, numerous worked examples, case studies, and support provided on a dynamic website, this text significantly expands concepts presented in the first edition.

    Introduction

    Historical Perspective and Moore’s Law

    Electrical Properties of Digital Integrated Circuits

    Computer-Aided Design and Verification

    Fabrication

    Semiconductors and Junctions

    The MOS Transistor

    MOS Gate Circuits

    Interconnect

    Dynamic CMOS

    Low-Power CMOS

    Bistable Circuits

    Memories

    Input/Output and Interface Circuits

     

    Fabrication

    Basic CMOS Fabrication Sequence

    Advanced Processing for High-Performance CMOS

    Lithography and Masks

    Layout and Design Rules

    Testing and Yield

    Packaging

    Burn-In and Accelerated Testing

     

    Semiconductors and p-n Junctions

    Crystal Structure of Silicon

    Energy Bands

    Carrier Concentrations

    Current Transport

    Carrier Continuity Equations

    Poisson’s Equation

    The p-n Junction

    Metal-Semiconductor Junctions

    SPICE Models

     

    The MOS Transistor

    The MOS Capacitor

    Threshold Voltage

    MOSFET Current-Voltage Characteristics

    Short-Channel MOSFETs

    MOSFET Design

    MOSFET Capacitances

    MOSFET Constant-Field Scaling

    SPICE MOSFET Models

    SPICE Demonstrations

     

    MOS Gate Circuits

    Inverter Static Characteristics

    Critical Voltages

    Dissipation

    Propagation Delays

    Fan-Out

    NOR Circuits

    NAND Circuits

    Exclusive OR (XOR) Circuit

    General Logic Design

    Pass Transistor Circuits

    SPICE Demonstrations

     

     

    Static CMOS

    Voltage Transfer Characteristic

    Load Surface Analysis

    Critical Voltages

    Crossover (Short-Circuit) Current

    Propagation Delays

    Inverter Rise and Fall Times

    Propagation Delays in Short-Channel CMOS

    Power Dissipation

    Fan-Out

    Circuit Delays as Functions of Fan-Out

    CMOS Ring Oscillator

    CMOS Inverter Design

    CMOS NAND Circuits

    CMOS NOR Circuits

    Other Logic Functions in CMOS

    74HC Series CMOS

    Pseudo NMOS Circuits

    Scaling of CMOS

    Latch-Up in CMOS

    SPICE Demonstrations

     

     

    Interconnect

    Capacitance of Interconnect

    Resistance of Interconnect

    Inductance of Interconnect

    Modeling Interconnect Delays

    Crosstalk

    Polysilicon Interconnect

    SPICE Demonstrations

    Practical Perspective

     

    Dynamic CMOS

    Rise Time

    Fall Time

    Charge Sharing

    Charge Retention

    Logic Design

    Alternative Form Using a p-MOS Pull-Up Network

    Cascading of Dynamic Logic Circuits

    Domino Logic

    Multiple-Output Domino Logic

    Zipper Logic

    Dynamic Pass Transistor Circuits

    CMOS Transmission Gate Circuits

    SPICE Demonstrations

    Practical Perspective

     

    Low-Power CMOS

    Low-Voltage CMOS

    Multiple Voltage CMOS

    Dynamic Voltage Scaling

    Active Body Biasing

    Multiple-Threshold CMOS

    Adiabatic Logic

    Silicon-on-Insulator

    Practical Perspective

     

    Bistable Circuits

    Set-Reset Latch

    SR Flip-flop

    JK Flip-flops

    Other Flip-flops

    Schmitt Triggers

    SPICE Demonstrations

    Practical Perspective

     

    Digital Memories

    Static Random Access Memory

    Dynamic Random Access Memory

    Read-Only Memory

    Programmable Read-Only Memory

    Erasable Programmable Read-Only Memory

    Electrically Erasable Programmable Read-Only Memory

    Flash Memory

    Other Nonvolatile Memories

    Access Times in Digital Memories

    Row and Column Decoder Design

    Practical Perspective

     

     

    Input/Output and Interface Circuits

    Input Electrostatic Discharge Protection

    Input Enable Circuits

    CMOS Output Buffers

    Tri-State Outputs

    Interface Circuits

    SPICE Demonstrations

     

    Appendices

    Biography

    John E. Ayers grew up eight miles from an integrated circuit design and fabrication facility, where he worked as a technician and first developed his passionate interest in the topic. After earning a BSEE degree from the University of Maine (Orono, Maine) in 1984, he worked as an integrated circuit test engineer for National Semiconductor (South Portland, Maine). He worked for six years at Rensselaer Polytechnic Institute (Troy, New York) and Philips Laboratories (Briarcliff, New York) on semiconductor material growth and characterization, earning the MSEE in 1987 and the PhDEE in 1990, both from Rensselaer Polytechnic Institute. Since then, he has been employed in academic research and teaching at the University of Connecticut (Storrs, Connecticut), where he has taught the course on digital integrated circuits for a number of years. He has been honored with the Electrical and Computer Engineering Best Teacher Award (2003–2004 and 2004–2005) and the School of Engineering Outstanding Teaching Award (2000–2001) and is a University of Connecticut Teaching Fellow (1999–2000). Ayers has authored more than 60 journal and conference papers as well as three books. He is a member of Eta Kappa Nu, Tau Beta Pi, and Phi Kappa Phi and is a senior member of the Institute of Electrical and Electronics Engineers. He lives in Ashford, Connecticut, and enjoys running, hiking, and bicycling with his wife and three children.