Sudeb Dasgupta, Brajesh Kumar Kaushik, Pankaj Kumar Pal
June 22, 2017
by CRC Press
Reference - 138 Pages - 39 Color & 49 B/W Illustrations
ISBN 9781498783590 - CAT# K30098
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This book focusses on the spacer engineering aspects of novel MOS-based device–circuit co-design in sub-20nm technology node, its process complexity, variability, and reliability issues. It comprehensively explores the FinFET/tri-gate architectures with their circuit/SRAM suitability and tolerance to random statistical variations.
Introduction to Nanoelectronics. Tri-gate FinFET Technology and Its Advancement. Dual-k Spacer Device Architecture and Its Electrostatics. Capacitive Analysis and Dual-k based Digital Circuit Design. Design Metric Improvement of Dual-k based SRAM Cell. Statistical Variability and Sensitivity Analysis.