Noise Coupling in System-on-Chip

Thomas Noulis

December 15, 2017 Forthcoming by CRC Press
Reference - 504 Pages
ISBN 9781498796774 - CAT# K30404
Series: Devices, Circuits, and Systems

USD$149.95

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Features

  • Covers substrate, interconnect and magnetic coupling from the silicon and device/on chip interconnect level to the package and the printed circuit board, with special focus on 3D Integrated circuits.
  • Thoroughly discusses substrate and interconnect magnetic crosstalk, 2D and 3D circuits noise coupling, TSV and simulation, sensing and optimization.
  • Features case studies related to all modern CMOS System on Chip products for mobile communications, automotive applications and readout front ends.
  • Chapters written by leading international experts in the field, novel methodologies are provided to identify noise coupling in silicon.
  • Summary

    Noise Coupling is the root-cause of the majority of Systems on Chip (SoC) product fails. The book discusses a breakthrough substrate coupling analysis flow and modelling toolset, addressing the needs of the design community. The flow provides capability to analyze noise components, propagating through the substrate, the parasitic interconnects and the package. Using this book, the reader can analyze and avoid complex noise coupling that degrades RF and mixed signal design performance, while reducing the need for conservative design practices. With chapters written by leading international experts in the field, novel methodologies are provided to identify noise coupling in silicon. It additionally features case studies that can be found in any modern CMOS SoC product for mobile communications, automotive applications and readout front ends.