1st Edition

Digital Integrated Circuits Design-for-Test Using Simulink and Stateflow

By Evgeni Perelroyzen Copyright 2007
    320 Pages 402 B/W Illustrations
    by CRC Press

    A current trend in digital design-the integration of the MATLAB® components Simulink® and Stateflow® for model building, simulations, system testing, and fault detection-allows for better control over the design flow process and, ultimately, for better system results. Digital Integrated Circuits: Design-for-Test Using Simulink® and Stateflow® illustrates the construction of Simulink models for digital project test benches in certain design-for-test fields.

    The first two chapters of the book describe the major tools used for design-for-test. The author explains the process of Simulink model building, presents the main library blocks of Simulink, and examines the development of finite-state machine modeling using Stateflow diagrams. Subsequent chapters provide examples of Simulink modeling and simulation for the latest design-for-test fields, including combinational and sequential circuits, controllability, and observability; deterministic algorithms; digital circuit dynamics; timing verification; built-in self-test (BIST) architecture; scan cell operations; and functional and diagnostic testing. The book also discusses the automatic test pattern generation (ATPG) process, the logical determinant theory, and joint test action group (JTAG) interface models.

    Digital Integrated Circuits explores the possibilities of MATLAB's tools in the development of application-specific integrated circuit (ASIC) design systems. The book shows how to incorporate Simulink and Stateflow into the process of modern digital design.

    INTRODUCTION

    SIMULINK®: DYNAMIC SYSTEM SIMULATION FOR MATLAB®
    Introduction
    Creating a Model
    Running a Simulation
    Analyzing Simulation Results
    Subsystems: Using Masks to Customize Blocks
    Reference Blocks
    Simulink Debugger

    STATEFLOW®: CREATING FINITE STATE MACHINE MODELS
    Introduction
    Creating Charts
    Entering a Stateflow Diagram
    Defining Events and Data
    Defining Stateflow Interfaces
    Exploring and Searching
    Debugging

    FAULT MODELING AND SIMULATION
    Fault Modeling
    Fault Simulation

    TESTABILITY ANALYSIS METHODS
    Combinational Controllability and Observability Analysis Models
    Sequential Controllability and Observability Analysis Models

    THE AUTOMATIC TEST PATTERN GENERATION (ATPG) PROCESS
    ATPG Fundamentals
    Combinational Circuit ATPG (Current-Based ATPG Algorithms for Combinational Circuits)

    TIMING VERIFICATION
    Logical Determinant Theory
    Digital Circuit Dynamics
    Model Building for Timing Verification

    SYSTEM AND EMBEDDED CORE TESTING
    Introduction
    Scan Path Architectures and Techniques
    System and Embedded Core Testing

    INDEX

    References appear at the end of each chapter.

    Biography

    Evgeni Perelroyzen