CMOS Nanoelectronics: Innovative Devices, Architectures, and Applications

Nadine Collaert

September 19, 2012 by Pan Stanford
Reference - 438 Pages - 25 Color & 211 B/W Illustrations
ISBN 9789814364027 - CAT# N10509


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  • Describes the benefits of FinFET, including reduced short-channel effects and leakage currents
  • Examines the challenges of FinFET, including gate stack design and source/drain engineering
  • Covers circuit-related aspects, such as the impact of variability on SRAM design, ESD design, and high-T operation
  • Explores the novel concept of the junctionless nanowire FET


This book covers one of the most important device architectures that have been widely researched to extend the transistor scaling: FinFET. Starting with theory, the book discusses the advantages and the integration challenges of this device architecture. It addresses in detail the topics such as high-density fin patterning, gate stack design, and source/drain engineering, which have been considered challenges for the integration of FinFETs. The book also addresses circuit-related aspects, including the impact of variability on SRAM design, ESD design, and high-T operation. It discusses a new device concept: the junctionless nanowire FET.