CMOS Nanoelectronics: Innovative Devices, Architectures, and Applications

CMOS Nanoelectronics: Innovative Devices, Architectures, and Applications

Published:
August 31, 2012 by Pan Stanford Publishing - 300 Pages
Editor(s):
Nadine Collaert, IMEC, Leuven, Belgium

Purchasing Options

Hardback
$149.95
Add to cart
ISBN 9789814364027
Cat# N10509
 

Features

  • Describes the benefits of FinFET, including reduced short-channel effects and leakage currents
  • Examines the challenges of FinFET, including gate stack design and source/drain engineering
  • Covers circuit-related aspects, such as the impact of variability on SRAM design, ESD design, and high-T operation
  • Explores the novel concept of the junctionless nanowire FET

Summary

This book covers one of the most important device architectures that have been widely researched to extend the transistor scaling: FinFET. Starting with theory, the book discusses the advantages and the integration challenges of this device architecture. It addresses in detail the topics such as high-density fin patterning, gate stack design, and source/drain engineering, which have been considered challenges for the integration of FinFETs. The book also addresses circuit-related aspects, including the impact of variability on SRAM design, ESD design, and high-T operation. It discusses a new device concept: the junctionless nanowire FET.

Table of Contents

General Introduction
Part 1: Integration of Multigate Devices (FinFET)
Introduction to Multigate Devices and Integration Challenges
Patterning Requirements for Multigate Devices
Gate Stack Design
Source/Drain Design: Reduction of Parasitic Resistance

Part 2: Circuit-Related Aspects
Variability and Its Implications for FinFET SRAM
High T Performance of FinFET
ESD and Multigate Devices

Part 3: Beyond FinFET
The Junctionless Nanowire Transistor
Transport in Nanostructures
Transport Spectroscopy of a Single Dopant in a Gated Silicon Nanowire
Thermionic Theory as a Tool for the Study of Transport in Doped and Undoped Si n-FINFETs Scaled Up to the Full Body Inversion Limit

Author Bio(s)

Nadine Collaert received her MS and PhD degrees in electrical engineering from the ESAT Department, Catholic University Leuven, Leuven, Belgium, in 1995 and 2000, respectively, where her PhD thesis was related to the modeling and characterization of a new transistor concept, the vertical Si/SiGe heterojunction MOSFET. She works as a senior researcher with IMEC, Leuven. She has been involved in the theory, design, and technology of FinFET-based multigate devices and emerging memory devices. Her current research interests include the design and integration of biosensors, transducers, and actuators and the integration and characterization of biocompatible materials, e.g., carbon-based materials. She has authored and coauthored more than 230 papers in international journals and conference proceedings.

Related Titles