Network-on-Chip: The Next Generation of System-on-Chip Integration

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ISBN 9781466565265
Cat# K16088



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  • Includes upto date survey
  • Provides excellent design component
  • Includes excellent analysis component
  • Provides examples of the chips that are implemented in industry and academia
  • Offers future direction of NoC research is also impressive


This book covers the important aspects of Network-on-Chip (NoC) design—communication infrastructure design, communication methodology, evaluation framework, mapping of applications onto NoC, and more. Apart from these, it also focuses on other upcoming NoC issues, such as low-power NoC design, signal integrity issues, NoC testing, reconfiguration, synthesis, and 3-D NoC design.

Table of Contents


Systems-on-Chip Integration and its Challenges

SoC to NoC: A Paradigm Shift

Research Issues in NoC Development

Exsisting NoC Examples



Interconnection Networks in NoC


Network Topologies

Switching Techniques

Routing Strategies

Flow Control Protocol

Quality-of-Service (QoS) Support

Network Interface (NI) Module



Architecture Design of Network – on- Chip


Switching Techniques and Packet Format

Asynchronous FIFO Design

GALS Style of Communication

Wormhole Router Architecture Design

Virtual Channel Router Architecture Design

Adaptive Router Architecture Design



Evolution of NoC Architectures

Evaluation Methodology of Performance and Cost Metrics of NoC

Traffic Modeling

Selection of Channel Width and Flit Size

Simulation Results and Analysis of MoT Network with Wormhole Router

Impact of FIFO Size and Placement in Energy and Performance of a Network

Performance and Cost Comparisons of different NoC Structures having Wormhole Router under Self- Similar Traffic

Simulations Results and Analysis of MoT Network with Virtual Channel Router

Performance and Cost Comparison of different NoC Structures having Virtual Channel Router

Limitations of Tree-based Topologies



Chapter 5: Application Mapping on NoC


The Mapping Problem

Integer Linear Programming (ILP) Formulation

Constructive Heuristics for Application Mapping

Constructive Heuristics with Iterative Improvement

Mapping using Discrete Particle Swarm Optimization

Performance Comparison



Lower Power Techniques for Network-on-Chip


Standard Low Power Methods for NoC Routers

Standard Low Power Methods for NoC Links

System Level Power Reduction



Single Integrity and Reliability of NoC


Sources of Fault in NoC

Permanent Fault Correction Techniques

Transient Fault Correction Techniques

Unified Coding Framework

Energy and Reliability Trade-off in Coding Technique



Testing of NoC Architectures


Testing Communication Fabric

Testing Cores



Application Specific NoC Synthesis


ASNoC Synthesis Problem

Literature Survey

System-level Floorplanning

Custom Interconnection Topology and Route Generation

ASNoC Synthesis with Flexible Router Placement



Reconfigurable Network-on-Chip Design


Literature Review

Topology Reconfiguration

Link Reconfiguration



3-D Intergration of NoC


3-D Integration: Pros and Cons

Design and Evaluation of 3-D NoC Architecture



Conclusions and Future Trends

Future Trends


Author Bio(s)

Santanu Kundu received his B.Tech. degree in Instrumentation Engineering from Vidyasagar University, India, in 2002. Thereafter, he served in industry for a couple of years as an electronics engineer and returned to academia for pursuing higher studies in 2004. He received M.Tech. in Instrumentation and Electronics Engineering from Jadavpur University, India, in 2006. Immediately after that he joined the Department of Electronics and Electrical Communication Engineering at Indian Institute of Technology, Kharagpur for pursuing Ph.D. with specialization in Microelectronics and VLSI Design. He received his PhD degree in 2011. Currently he is working as a SoC Design Engineer at LSI India R&D Pvt. Ltd., Bangalore. His research interests include Network-on-Chip Architecture Design in 2-D and 3-D environments, Performance and Cost Evaluation, Signal Integrity in nanometer regime, Fault Tolerant schemes, and Power-Performance-Reliability trade-off.

Santanu Chattopadhyay is currently a Professor in the Department of Electronics and Electrical Communication Engineering at Indian Institute of Technology, Kharagpur. He received his B.E. degree in Computer Science and Technology from Calcutta University (B.E. College) in 1990. In 1992 and 1996 he received his M. Tech in Computer and Information Technology and Ph.D. in Computer Science and Engineering degrees respectively, both from Indian Institute of Technology, Kharagpur. Before joining IIT Kharagpur, he was a faculty member at B.E. College, Howrah, India, and Indian Institute of Technology, Guwahati. His research interests include CAD tools for low power circuit design and test, System-on-Chip testing, Network-on-Chip design and test. He has more than hundred publications in refereed international journals and conferences. He is the co-author of the book on "Additive Cellular Automata – Theory and Applications", published by the IEEE Computer Society Press in 1997. He has also written text books on "Compiler Design", "System Software", and "Embedded System Design", all from PHI Learning, India. He is a member of the Editorial Board of the journal IET Circuits, Devices and Systems.

Editorial Reviews

"What makes this book special as compared to the current literature in the field is that it provides a complete picture of NoC architectures. In fact, current books in the context of NoCs are usually specific and presuppose a basic knowledge of NoC architectures. Conversely, this book provides a complete guide for both unskilled readers and researchers working in the area, to acquire not only the basic concepts but also the advanced techniques for improving power, cost and performance metrics of the on-chip communication system."
—Maurizio Palesi, Kore University, Italy