Multicore Technology: Architecture, Reconfiguration, and Modeling

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ISBN 9781439880630
Cat# K13790



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ISBN 9781439880647
Cat# KE13941



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  • Includes contributions by top academics and researchers in the field
  • Covers the background of the technology, examples of various configurations, and questions that require further research
  • Contains information on multicore reconfiguration and optimization
  • Targets both high-performance computing (HPC) and embedded communities
  • Provides a survey of the state of the art in the field of multicore technology


The saturation of design complexity and clock frequencies for single-core processors has resulted in the emergence of multicore architectures as an alternative design paradigm. Nowadays, multicore/multithreaded computing systems are not only a de-facto standard for high-end applications, they are also gaining popularity in the field of embedded computing.

The start of the multicore era has altered the concepts relating to almost all of the areas of computer architecture design, including core design, memory management, thread scheduling, application support, inter-processor communication, debugging, and power management. This book gives readers a holistic overview of the field and guides them to further avenues of research by covering the state of the art in this area. It includes contributions from industry as well as academia.

Table of Contents

Architecture and Design Flow

MORA: High-Level FPGA Programming Using a Many-Core Framework
Wim Vanderbauwhede, Sai Rahul Chalamalasetti, and Martin Margala

Implementing Time-Constrained Applications on a Predictable MPSoc
Sander Stuijk, Akash Kumar, Roel Jordans, and Henk Corporaal

SESAM: A Virtual Prototyping Solution to Design Multicore Architectures
Nicolas Ventroux, Tanguy Sassolas, Alexandre Guerre, and Caaliph Andriamisaina

Parallelism and Optimization

Verified Multicore Parallelism Using Atomic Verifiable Operations
Michal Dobrogost, Christopher Kumar Anand, and Wolfram Kahl

Accelerating Critical Section Execution with Multicore Architectures
M. Aater Suleman and Onur Mutlu

Memory Systems

TMbox: A Flexible and Reconfigurable Hybrid Transactional Memory System
Nehir Sonmez, Oriol Arcas, Osman S. Unsal, Adrián Cristal, and Satnam Singh

Omer Khan, Mieszko Lis, Keun Sup Shim, Myong Hyon Cho, and Srinivas Devadas

CAFÉ: Cache-Aware Fair and Efficient Scheduling for CMPs
Richard West, Puneet Zaroo, Carl A. Waldspurger, and Xiao Zhang


Software Debugging Infrastructure for Multicore Systems-on-Chip
Bojan Mihajlović, Warren J. Gross, and Željko Žilić


On Chip Interconnects for Multicore Architectures
Prasun Ghosal and Soumyajit Poddar

Routing in Multicore NoCs
Prasun Ghosal and Tuhin Subhra Das

Efficient Topologies for 3-D Networks-on-Chip
Mohammad Ayoub Khan and Abdul Quaiyum Ansari

Network-on-Chip Performance Evaluation Using an Analytical Method
Sahar Foroutan, Abbas Sheibanyrad, and Frédéric Pétrot



Author Bio(s)