Communication Architectures for Systems-on-Chip

Communication Architectures for Systems-on-Chip

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Features

  • Includes a comprehensive study of state-of-the-art communication architectures for SoC
  • Offers a practical review of industry standards and manufactured implementations
  • Surveys more recent approaches and technologies to convey industry developments and trends
  • Presents case studies to aid designers’ conception of new architectures
  • Provides chapter-end conclusions, glossaries, bibliographies, and a list of references

Summary

A presentation of state-of-the-art approaches from an industrial applications perspective, Communication Architectures for Systems-on-Chip shows professionals, researchers, and students how to attack the problem of data communication in the manufacture of SoC architectures.

With its lucid illustration of current trends and research improving the performance, quality, and reliability of transactions, this is an essential reference for anyone dealing with communication mechanisms for embedded systems, systems-on-chip, and multiprocessor architectures—or trying to overcome existing limitations. Exploring architectures currently implemented in manufactured SoCs—and those being proposed—this book analyzes a wide range of applications, including:

  • Well-established communication buses
  • Less common networks-on-chip
  • Modern technologies that include the use of carbon nanotubes (CNTs)
  • Optical links used to speed up data transfer and boost both security and quality of service (QoS)

The book’s contributors pay special attention to newer problems, including how to protect transactions of critical on-chip information (personal data, security keys, etc.) from an external attack. They examine mechanisms, revise communication protocols involved, and analyze overall impact on system performance.

Table of Contents

Introduction, J.L. Ayala

Today’s market for systems-on-chip

Basics of the system-on-chip design

Open issues

 

Communication Buses, P.G. del Valle and J.L. Ayala

The AMBA Interface

Sonics SMART Interconnects

CoreConnect Bus

STBus

FPGA on-chip buses

Open Standards

WishBone

Other specific buses

Security

 

NoC Architectures, M. Ruggiero

Advantages of the NoC Paradigm

Challenges of the NoC Paradigm

Principles of NoC Architecture

Basic Building Blocks of a NoC

Available NoC Implementations and Solutions

 

Quality-of-Service in NoCs, F. Angiolini and S. Murali

Architectures for QoS

 

Emerging Interconnect Technologies, D. Sacchetto, M.H. Ben-Jamaa, B. Shashi Kanth, and F. Sun

Optical Interconnects

Plasmonic Interconnects

Silicon Nanowires

Carbon Nanotubes

3D Integration Technology

 

HeTERO: Hybrid Topology Exploration for RF based On Chip Networks, S. Eachempati, R. Das, V. Narayanan, Y. Xie, S. Datta, and C.R. Das

RF-Interconnect

State-of-art Topologies

RF-Topology Modeling

RF-based Topologies

Experimental Setup

Results

Applications

Related Work

 

Intra-/Inter-Chip Optical Communications, B. Garcia-Camara

Photonic Components for On-chip Optical Interconnects

Why optical links? Comparison of electrical and optical interconnects

Photonic Networks

New optical nanocircuits based on metamaterials

Present and Future of the Intra-/Inter-Chip Optical Interconnections

 

Security Issues in SoC Communication, J.M. Moya, J.M. de Goyeneche, and P. Malagon

Power Analysis Attacks

Logic-level DPA-aware Techniques

Architecture-level DPA-aware Techniques

Algorithm-level DPA-aware Techniques

Validation

Traps and Pitfalls

Editor Bio(s)

Jose L. Ayala got a M.S. in Telecommunications Engineering from Politecnica University of Madrid in 2001, and a M.S. in Physics from the Open University of Spain in 2002. After that, he pursued his Ph.D on Electronic Engineering at the Department of Electrical Engineering of the Politecnica University of Madrid. He is currently an Associate Professor at the Department of Computer Architecture of the Complutense University of Madrid.

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