Designing Network On-Chip Architectures in the Nanoscale Era

Designing Network On-Chip Architectures in the Nanoscale Era

Series:
Published:
Content:
Editor(s):
Free Standard Shipping

Purchasing Options

Hardback
$109.95 $87.96
ISBN 9781439837108
Cat# K11679
Add to cart
SAVE 20%
eBook (VitalSource)
$109.95 $76.97
ISBN 9781439837115
Cat# KE11686
Add to cart
SAVE 30%
eBook Rentals
Other eBook Options:
 
 

Features

  • Presents the foundations of NoC technology, emphasizing industrial applicability
  • Covers established and alternative design principles and guidelines
  • Explores design techniques that meet the requirements of emerging research and development, such as vertical integration and variation-tolerant design
  • Illustrates the techniques through real design examples, including those from the semiconductor industry in the CMP and MPSoC domains

Summary

Going beyond isolated research ideas and design experiences, Designing Network On-Chip Architectures in the Nanoscale Era covers the foundations and design methods of network on-chip (NoC) technology. The contributors draw on their own lessons learned to provide strong practical guidance on various design issues.

Exploring the design process of the network, the first part of the book focuses on basic aspects of switch architecture and design, topology selection, and routing implementation. In the second part, contributors discuss their experiences in the industry, offering a roadmap to recent products. They describe Tilera’s TILE family of multicore processors, novel Intel products and research prototypes, and the TRIPS operand network (OPN). The last part reveals state-of-the-art solutions to hardware-related issues and explains how to efficiently implement the programming model at the network interface. In the appendix, the microarchitectural details of two switch architectures targeting multiprocessor system-on-chips (MPSoCs) and chip multiprocessors (CMPs) can be used as an experimental platform for running tests.

A stepping stone to the evolution of future chip architectures, this volume provides a how-to guide for designers of current NoCs as well as designers involved with 2015 computing platforms. It cohesively brings together fundamental design issues, alternative design paradigms and techniques, and the main design tradeoffs—consistently focusing on topics most pertinent to real-world NoC designers.

Table of Contents

NoC TECHNOLOGY
Introduction to Network Architectures
, José Duato
The Role of Interconnects in the Internet Era
Basic Network Architecture
Heterogeneity
Sources of Heterogeneity

Switch Architecture, Giorgos Dimitrakopoulos and Davide Bertozzi
Introduction
How Packets Move between Switches?
Baseline Wormhole Switch
Virtual Channels
Modular Switch Construction
Conclusions

Logic-Level Implementation of Basic Switch Components, Giorgos Dimitrakopoulos
Introduction
Buffer Memory
Crossbar Design Options
Switch/VC Allocators
Conclusions

Topology Exploration, Francisco Gilabert, Daniele Ludovici, María Engrácia Gómez, and Davide Bertozzi
Introduction
The High Level View
Physical Design Pitfalls
16-Tile Systems
64-Tile Systems
The Performance Prediction Gap
Conclusions

Routing Algorithms and Mechanisms, José Flich, Samuel Rodrigo, Antoni Roca, and Simone Medardoni
Basic Routing Concepts
Current Proposals for Routing in NoCs
Routing Restrictions as a Way to Effective Routing Implementation
Unicast Logic-Based Distributed Routing
SBBM: Signal Bit-Based Multicast
eLBDR: Gathering Unicast and Broadcast Implementations
Future Challenges for Routing

The Synchronization Challenge, Davide Bertozzi, Alessandro Strano, Daniele Ludovici, Vasileios Pavlidis, Federico Angiolini, and Milos Krstic
Introduction
The System Architecture
Building Blocks for GALS NoC Architectures
NoC Clocking and Synchronization in 3-D Stacked ICs
Conclusions

THE INDUSTRIAL PERSPECTIVE
Networks of the Tilera Multicore Processor
, David Wentzlaff, Patrick Griffin, Henry Hoffmann, Liewei Bao, Bruce Edwards, Carl Ramey, Matthew Mattina, Chyi-Chang Miao, John F. Brown III, and Anant Agarwal
Introduction
TILE Processor Architecture Overview
Interconnect Hardware
Interconnect Software
Applications
Future Architectures
Conclusion

On-Chip Interconnect Trade-Offs for Tera-Scale Many-Core Processors, Mani Azimi, Donglai Dai, Akhilesh Kumar, and Aniruddha S. Vaidya
Introduction
Evolution of Interconnects in Intel Processors: External to Internal
A Low-Latency Flexible 2-D On-Chip Interconnect
Summary and Conclusions

The TRIPS OPN: A Processor Integrated NoC for Operand Bypass, Paul V. Gratz and Stephen W. Keckler
Introduction
Related Work
TRIPS Processor Overview
OPN Design and Implementation
OPN Evaluation
Summary

UPCOMING TRENDS
Network Interface Design for Explicit Communication in Chip Multiprocessors
, Stamatis Kavadias, Manolis Katevenis, and Dionisios Pnevmatikatos
Network Interface Evolution and Outlook
Processor-Integrated Network Interfaces
NI Integration at Top Memory Hierarchy Levels
NI Control Registers and Virtualization
Communication and Data Synchronization Mechanisms
Case Study: Task Synchronization and Scheduling Support in the SARC Network Interface
Conclusions and Future Perspectives

Three-Dimensional On-Chip Interconnect Architectures, Soumya Eachempati, Dongkook Park, Reetuparna Das, Asit K. Mishra, Vijaykrishnan Narayanan, Yuan Xie, and Chita Das
Introduction
3-D Router Design
Related Work
3-D NoC Router Architectures
Performance Evaluation
Conclusions

Congestion Management and Process Variation, José Flich, Federico Silla, Carles Hernández, and Mario Lodde
Traffic Analysis for CMP Systems
Congestion Management
Variability in NoCs
Conclusions

Appendix: Switch Models, Davide Bertozzi, Simone Medardoni, Antoni Roca, José Flich, Federico Silla, and Francisco Gilabert
Case Study: The xpipesLite Switch Architecture
gNoC: A Switch Design for CMP Systems

Bibliography

Editor Bio(s)

José Flich is an associate professor of computer architecture and technology at the Technical University of Valencia. Dr. Flich is the coordinator of the EU-funded NaNoC project; co-chair of the CAC, CASS, and INA-OCMC workshops; and co-developer of RECN, the only truly scalable congestion management technique proposed to date. He is also associate editor of the IEEE Transactions on Parallel and Distributed Systems. His research interests include high-performance interconnection networks for multiprocessor systems, clusters of workstations, and networks on-chip.

Davide Bertozzi is an assistant professor and leader of the Multi-Processor Systems-On-Chip research group at the University of Ferrara. Dr. Bertozzi is the general chair of the INA-OCMC workshop and an editorial board member of IET Computers & Digital Techniques. His research interests encompass multi-core digital integrated systems, with an emphasis on all aspects of system interconnect design.

Editorial Reviews

… a timely and welcome addition to the wide spectrum of available NoC literature … above and beyond a simple overview of research ideas and/or design experiences. The book covers in-depth architectural and implementation concepts and gives clear guidelines on how to design the key network components. … [it] teaches some hard lessons from the design trenches. In addition, the book covers some of the hottest upcoming research and development trends, such as vertical integration and variation-tolerant design. The editors put enormous effort in orchestrating the content for uniformity and in minimizing overlaps between chapters, while maintaining a solid logical flow. … a much needed ‘how-to’ guide and an ideal stepping stone for the next ten years of NoC evolution.
—From the Foreword by Luca Benini, Università di Bologna and STMicroelectronics, Italy

 
Textbooks
Other CRC Press Sites
Featured Authors
STAY CONNECTED
Facebook Page for CRC Press Twitter Page for CRC Press You Tube Channel for CRC Press LinkedIn Page for CRC Press Google Plus Page for CRC Press Pinterest Page for CRC Press
Sign Up for Email Alerts
© 2014 Taylor & Francis Group, LLC. All Rights Reserved. Privacy Policy | Cookie Use | Shipping Policy | Contact Us