1st Edition

Design of Low-Power Coarse-Grained Reconfigurable Architectures

By Yoonjin Kim, Rabi N. Mahapatra Copyright 2010
    224 Pages 117 B/W Illustrations
    by CRC Press

    224 Pages 117 B/W Illustrations
    by CRC Press

    Coarse-grained reconfigurable architecture (CGRA) has emerged as a solution for flexible, application-specific optimization of embedded systems. Helping you understand the issues involved in designing and constructing embedded systems, Design of Low-Power Coarse-Grained Reconfigurable Architectures offers new frameworks for optimizing the architecture of components in embedded systems in order to decrease area and save power. Real application benchmarks and gate-level simulations substantiate these frameworks.

    The first half of the book explains how to reduce power in the configuration cache. The authors present a low-power reconfiguration technique based on reusable context pipelining that merges the concept of context reuse into context pipelining. They also propose dynamic context compression capable of supporting required bits of the context words set to enable and the redundant bits set to disable. In addition, they discuss dynamic context management for reducing power consumption in the configuration cache by controlling a read/write operation of the redundant context words.

    Focusing on the design of a cost-effective processing element array to reduce area and power consumption, the second half of the text presents a cost-effective array fabric that uniquely rearranges processing elements and their interconnection designs. The book also describes hierarchical reconfigurable computing arrays consisting of two reconfigurable computing blocks with two types of communication structure. The two computing blocks share critical resources, offering an efficient communication interface between them and reducing the overall area. The final chapter takes an integrated approach to optimization that draws on the design schemes presented in earlier chapters. Using a case study, the authors demonstrate the synergy effect of combining multiple design schemes.

    Introduction
    Coarse-Grained Reconfigurable Architecture (CGRA)
    Objective and Approach
    Overview of the Book’s Contents

    Trends in CGRA
    Introduction
    Architecture
    Design Space Exploration
    Code Compilation and Mapping
    Physical Implementation

    CGRA for High Performance and Flexibility
    Performance versus Flexibility for Embedded Systems
    Performance Evaluation Examples

    Base CGRA Implementation
    Introduction
    Reconfigurable Array Architecture Coupling with Processor
    Base Reconfigurable Array Architecture
    Breakdown of Area and Delay Cost

    Power Consumption in CGRA
    Introduction
    Breakdown of Power Consumption in CGRA
    Necessity of Power-Conscious CGRA Design

    Low-Power Reconfiguration Technique
    Introduction
    Motivation
    Individual Approaches to Reduce Power in Configuration Cache
    Integrated Approach to Reduce Power in Configuration Cache
    Application Mapping Flow
    Experiments

    Dynamic Context Compression for Low-Power CGRA
    Introduction
    Preliminary
    Motivation
    Design Flow of Dynamically Compressible Context Architecture
    Experiments

    Dynamic Context Management for Low-Power CGRA
    Introduction
    Motivation
    Dynamic Context Management
    Experiments

    Cost-Effective Array Fabric
    Introduction
    Preliminary
    Cost-Effective Reconfigurable Array Fabric
    Experiments

    Hierarchical Reconfigurable Computing Arrays
    Introduction
    Motivation
    Computing Hierarchy in CGRA
    Experiments

    Integrated Approach to Optimize CGRA
    Combination among the Cost-Effective CGRA Design Schemes
    Case Study for Integrated Approach
    Potential Combinations and Expected Outcomes

    Bibliography

    Index

    A Summary appears at the end of each chapter.

    Biography

    Yoonjin Kim is an assistant professor in the Department of Computer Science at Sookmyung Women’s University in Seoul, South Korea. Dr. Kim was previously a senior R&D staff member at Samsung Advanced Institute of Technology in Yongin, South Korea. He earned his Ph.D. in computer engineering from Texas A&M University. His research interests include embedded systems, computer architecture, VLSI/system-on-chip design, and hardware/software co-design.

    Rabi N. Mahapatra is a professor in the Department of Computer Science and Engineering and director of the Embedded Systems and Codesign Laboratory at Texas A&M University in College Station. He is an associate editor of the ACM Transactions on Embedded Computing and an editorial board member of the International Journal on Information and Communication Technology. Dr. Mahapatra is also founder and chairman of the Bhubaneswar Institute of Technology (BIT) in India. His research interests include network on chip, system-on-chip reliability, low-power IP lookup architectures, and intention-based searching.