Technological advancement in chip development, primarily based on the downscaling of the feature size of transistors, is threatening to come to a standstill as we approach the limits of conventional scaling. For example, when the number of electrons in a device's active region is reduced to less than ten electrons (or holes), quantum fluctuation errors will occur, and when gate insulator thickness becomes too insignificant to block quantum mechanical tunneling, unacceptable leakage will occur. Fortunately, there is truth in the old adage that whenever a door closes, a window opens somewhere else. In this case, that window opening is nanotechnology.
Silicon Nanoelectronics takes a look at at the recent development of novel devices and materials that hold great promise for the creation of still smaller and more powerful chips. Silicon nanodevices are positoned to be particularly relevant in consideration of the existing silicon process infrastructure already in place throughout the semiconductor industry and silicon's consequent compatibility with current CMOS circuits. This is reinforced by the nearly perfect interface that can exist between natural oxide and silicon.
Presenting the contributions of more than 20 leading academic and corporate researchers from the United States and Japan, Silicon Nanoelectronics offers a comprehensive look at this emergent technology. The text includes extensive background information on the physics of silicon nanodevices and practical CMOS scaling. It considers such issues as quantum effects and ballistic transport and resonant tunneling in silicon nanotechnology. A significant amount of attention is given to the all-important silicon single electron transistors and the devices that utilize them.
In offering an update of the current state-of-the-art in the field of silicon nanoelectronics, this volume serves well as a concise reference for students, scientists, engineers, and specialists in various fields, including electron device technology, solid-state physics, and nanotechnology.
Physics of Silicon Nanodevices D. K. Ferry, R. Akis, M. J. Gilbert, and S. M. Ramey
Small MOSFETs. The Simple One-Dimensional Theory. Ballistic Transport in the MOSFET. Granularity. Quantum Behavior in the Device. The Effective Potential. Effective Carrier Wave Packet. Statistical Considerations. Quantum Simulations. The Device Structure. Wave Function and Technique. Results. Quantum Dot Single-Electron Devices. Many-Body Interactions.
Practical CMOS Scaling David J. Frank CMOS Technology. Overview. Current CMOS Device Technology. International Technology Roadmap for Semiconductors (ITRS). Projections. Scaling Principles. General Scaling. Characteristic Scale Length. Exploratory Technology. New Materials. Fully Depleted SOI. Double-Gate and Multiple-Gate FET Structures. Limits to Scaling. Quantum Mechanics. Atomistic Effects. Thermodynamic Effects. Practical Considerations. Power-Constrained Scaling Limits.
The Scaling Limit of MOSFETs due to Direct Source-Drain Tunneling Hisao Kawaura. EJ-MOSFETs. Concept of EJ-MOSFETs. Fabrication of the Device Structure. Basic Operation. Direct Source-Drain Tunneling. Detection of the Tunneling Current. Numerical Study of the Tunneling Current. The Scaling Limit of MOSFETs. Estimation of Direct Source-Drain Tunneling in MOSFETs. Future Trends in Post-6-nm MOSFETs.
Quantum Effects in Silicon Nanodevices Toshiro Hiramoto. Quantum Effects in MOSFETs. Band Structures of Silicon. Surface Quantization. Carrier Confinement in Thin SOI MOS Structures. Mobility of Confined Carriers. Influences of Quantum Effects in MOSFETs. Threshold Voltage Increase in Bulk MOSFETs. Threshold Voltage Increase in FD-SOI MOSFETs. Mobility in Ultrathin FD-SOI MOSFETs. Quantum Effects in Ultranarrow Channel MOSFETs. Advantage of Quantum Effects in Ultranarrow Channel MOSFETs. Threshold Voltage Increase in n-Type Narrow Channel MOSFETs. Threshold Voltage Increase in n-Type and p-Type Narrow Channel MOSFETs. Threshold Voltage Adjustment Using Quantum Effects. Mobility Enhancement due to Quantum Effects.
Ballistic Transport in Silicon Nanostructures Hiroshi Mizuta, Katsuhiko Nishiguchi and Shunri Oda. Ballistic Transport in Quantum Point Contacts. Ballistic Transport in Ultra-Short Channel Vertical Silicon Transistors. Fabrication of Nanoscale Vertical FETs. Conductance Quantization in Nanoscale Vertical FETs. Characteristics under a Magnetic Field. Effects of Cross-Sectional Channel Geometries. Summary and Future Subjects.
Resonant Tunneling in Si Nanodevices Michiharu Tabe, Hiroya Ikeda, and Yasuhiko Ishikawa. Outline of Resonant Tunneling. Early Work on Resonant Tunneling. Resonant Tunneling in Si-Based Materials - Si/SiGe and Si/SiO. Quantum Confinement Effect in a Thin Si Layer. Double-Barrier Structures of SiO. /Si/SiO. Formed by Anisotropic Etching. Resonant Tunneling in SiO. /Si/SiO. Fabrication of an RTD. Resonant Tunneling in the Low Voltage Region. Hot-Electron Storage in the High-Voltage Region. Switching of Tunnel-Modes: Comparison with a Single Barrier. Zero-Dimensional Resonant Tunneling. Coexistence of Coulomb Blockade and Resonant Tunneling. Fabrication of a SiO. /Si-Dots/SiO. Structure. I-VCharacteristics of an SiO. /Si-Dots/SiO. Tunnel Diode.
Silicon Single-Electron Transistor and Memory L. Jay Guo. Quantum Dot Transistor. Theoretical Background. Energy of the Quantum Dot System. Conductance Oscillation and Potential Fluctuation. Transport under Finite Temperature and Finite Bias. Device Structure and Fabrication. Experimental Results and Analysis. Single-Electron Quantum-Dot Transistor. Single-Hole Quantum-Dot Transistor. Transport Characteristics under Finite Bias. Transport through Excited States. Artificial Atom. Single Charge Trapping. Introduction to Memory Devices. Floating Gate Scheme. Single-Electron MOS memory (SEMM). Structure of SEMM. Fabrication Procedure. Experimental Observations. Analysis. Effects of Trap States. Effect of Thicker Tunnel Oxide.
Silicon Memories Using Quantum and Single-Electron Effects.
Sandip Tiwari. Single-Electron Effect. Single-Electron Transistors and Their Memories. Memories by Scaling Floating Gates of Flash Structures. Modeling of Transport: Tunneling. Tunneling in Oxide. Quantum Kinetic Equation. Carrier Statistics and Charge Fluctuations. Experimental Behavior of Memories. Percolation Effects. Limitations in Use of Field Effect. Confinement and Random Effects in Semiconductors. Variances due to Dimensions. Limits due to Tunneling. Tunneling in Oxide. Tunneling in Silicon. Can We Avoid Use of Collective Phenomena?
SESO Memory Devices K. Yano. How Nanotechnologies Solve Real Problems. New Direction of Electronics. Conventional Memory Technologies. Classification of Conventional Memories. Origin of DRAM Power Consumption. Bandgap Enlargement in Nanosilicon. SESO Transistor. History: Single-Electron Devices to SESO. Fabricated SESO Transistor. SESO Memory. Memory-Technology Comparison. SESO as On-Chip RAM Component.
Few Electron Devices and Memory Circuits Kazuo Nakazato and Haroon Ahmed. Current Semiconductor Memories. Limitations of the DRAM. DRAM Gain Cell. A New DRAM Gain Cell - The PLEDM. PLEDTR. PLEDM Cell. Single-Electron Memory. Single-Electron Devices. Operation Principle of Single-Electron Memory. Local Stability. Global Stability. Experimental Single-Electron Memory. First Experimental Single-Electron Memory. Silicon Single-Electron Memory. Single-Electron Memory Array.
Single-Electron Logic Devices Yasuo Takahashi, Yukinori Ono, Akira Fujiwara, and
Hiroshi Inokawa. Single-Electron Transistor (SET). Fabrication of Si SETs. Logic Circuit Applications of SETs. Fundamentals of SET Logic. Merged SET and MOSFET Logic. CMOS-Type Logic Circuit. Pass-Transistor Logic. Multigate SET. Multiple-Valued Operation.
Each chapter offers an introduction and concludes with acknowledgements, references, and a summary
"The book represents a good reference for engineers, scientists, and postgraduate students interested in the most recent silicon nanoelectronic developments."
– Gaetano Palumbo, in IEEE Circuits & Devices Magazine, September/ October 2006, Vol. 22, No. 5
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