Muhammad Yasir Qadri
Mr. Yasir is currently involved in research in the area of Multiprocessor System on-Chip (MPSoC) reconfiguration schemes based on power efficient throughput management. The main aim of the research is to propose an artificial intelligence based scheme for MPSoCs to realize, hitting the rock bottom of power consumption and attaining height of performance.
Subjects: Computer Science & Engineering
Biography
Specialties:I have good understanding of various processor architectures, and am currently working on an innovative multicore re-configurable architecture design. Can be able to suggest improvements in existing architectures/suggest new ones and may help in Hardware/Software Co-design issues.Education
-
PhD, University of Essex, UK, 2007-2010
Areas of Research / Professional Expertise
-
Reconfigurable Architectures, Multicore Systems, MPSoC, Fuzzy Logic, Design Space Exploration, Optimization.
Websites
Books
News
Received Research Funding of PKR. 27.16 Million from ICTR&D Fund Pakistan
By: Muhammad Yasir Qadri
Subjects: Computer Science & Engineering
A Multicore Reconfigurable Processor Platform for Energy and Throughput Aware Applications(Link)
July 2013
The saturation of design
complexity and clock frequencies for single core processors have
resulted in the emergence of multicore architectures as an
alternative design paradigm. In the recent trends,
multicore/multithreaded computing systems are not only a de facto
standard for high-end applications but are gaining popularity in
the field of embedded computing. The advanced level research on
multicore architectures requires the development of a high-end test
bed for the exploration of hardware and software. Therefore, we
propose an FPGA based multicore reconfigurable architecture that
will support MS and PhD level research and development in the areas
of multicore-processing including core design, memory management,
thread scheduling, application support, inter-processor
communication, debugging, power management, run-time
reconfiguration, real-time applications and many more.
The scope of this research project will include the development of
an FPGA based reconfigurable multicore architecture that will
support runtime reconfiguration of cache size and associativity,
number of cores and operating frequency. Using the performance
counters we will be able to have a feedback of energy consumption,
application throughput and cache miss rate. The project will also
include the development of Fuzzy logic, Neural Nets, Game
Programming or similar Artificial Intelligence (AI) based algorithm
to strike a balance between throughput and energy consumption of
work-load